VHDL Code for 1-bit Comparator

1-bit comparator using behavioral  style:

entity comp is

          port ( a: in bit_vector(0 to 1);e: out bit_vector(2 downto 0));

end entity;

architecture comp_beha of comp is

begin

          process(a)

          variable temp : bit;

          begin

                   case a is

                             when "00" => e <="100";

                             when "01" => e <="010";

                             when "10" => e <="001";

                             when "11" => e <="100";

                             when others => null;

                             end case;

          end process;

          end architecture;

1-bit comparator using structural style model:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity COMP_1 is

           port(

                    A : in STD_LOGIC;

                    B : in STD_LOGIC;

                    E : out STD_LOGIC;

                    L : out STD_LOGIC;

                    G : out STD_LOGIC

               );

end COMP_1;

architecture COMP_STRU of COMP_1 is

component xnor2

          port(l, m: in STD_LOGIC; n: out STD_LOGIC);

end component;

component and2

          port(x, y: in STD_LOGIC; z: out STD_LOGIC);

end component;

component inv

          port( s: in STD_LOGIC; t: out STD_LOGIC);

end component;

   for A1:and2 use entity work.and2(and2);             

          for X1:xnor2 use entity work.xnor2(xnor2);

          for I1:inv use entity work.inv(inv);

signal abar,bbar: STD_LOGIC;

begin

          I1: INV PORT MAP( A, ABAR);

          I2: INV PORT MAP (B,BBAR);

          X1: xnor2 port map ( a, b, e);

          A1: and2 port map( abar,b,l);

          A2: and2 port map(a,bbar,g);

end COMP_STRU;