VHDL CODE FOR MULTIPLEXER WITH DATA FLOW MODEL:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX_4X1 is
port(
A : in
STD_LOGIC;
B : in
STD_LOGIC;
C : in
STD_LOGIC;
D : in
STD_LOGIC;
S : in
STD_LOGIC_VECTOR(1 down to 0);
Y : out
STD_LOGIC
);
end MUX_4X1;
architecture MUX_DATA of
MUX_4X1 is
begin
Y<= A WHEN S(1)='0' AND
S(0)='0' ELSE
B WHEN S(1)='0' AND S(0)='1' ELSE
C WHEN S(1)='1' AND S(0)='0' ELSE
D WHEN S(1)='1' AND S(0)='1' ;
end MUX_DATA;
VHDL CODE FOR MULTIPLEXER WITH BEHAVIORAL-MODEL DESIGN:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX_4X1 is
port(
A : in
STD_LOGIC;
B : in
STD_LOGIC;
C : in
STD_LOGIC;
D : in
STD_LOGIC;
S : in
STD_LOGIC_VECTOR(1 down to 0);
Y : out
STD_LOGIC
);
end MUX_4X1;
architecture MUX_BEH of
MUX_4X1 is
begin
PROCESS(A,B,C,D,S)
BEGIN
CASE S IS
WHEN "00" => Y<= A;
WHEN "01" => Y<= B;
WHEN "10" => Y<= C;
WHEN "11" => Y<= D;
WHEN OTHERS => NULL;
END CASE;
END
PROCESS;
end MUX_BEH;
VHDL CODE FOR MULTIPLEXER WITH STRUCTURAL STYLE MODEL:
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity MUX4X1 is
port(
A : in
STD_LOGIC;
B : in
STD_LOGIC;
C : in
STD_LOGIC;
D : in
STD_LOGIC;
S0 : in
STD_logic;
S1 : IN
STd_logic;
Y : out
STD_LOGIC
);
end MUX4X1;
architecture MUX_STRU of
MUX4X1 is
COMPONENT AND3
PORT( L,M,O: IN STD_LOGIC; N: OUT STD_LOGIC);
END COmponent;
COMPONENT OR4
PORT( H,I,J,K: IN STD_LOGIC; H1: OUT STD_LOGIC);
END COmponent;
COMPONENT INV_1
PORT( E: IN STD_LOGIC; F: OUT STD_LOGIC);
END COmponent;
for v0:and3 use entity work.and3(and3);
for v4:or4 use entity work.or4(or4);
for u0:inv_1 use entity work.inv_1(inv_1);
SIGNAL S0BAR,S1BAR,W,X,G,Z:
STD_LOGIC;
BEGIN
U0: INV_1 PORT MAP (S0,S0BAR);
U1: INV_1 PORT MAP (S1,S1BAR);
V0: AND3 PORT MAP (A,S1BAR,S0BAR,W);
V1: AND3 PORT MAP (B,S1BAR,S0 ,X);
V2: AND3 PORT MAP (C,S1 ,S0BAR,G);
V3: AND3 PORT MAP (D,S1 ,S0 ,Z);
V4: OR4 PORT MAP ( W,X,G,Z,Y);
end MUX_STRU;
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