VLSI Design - Question Bank

EC 2354 VLSI DESIGN

L-1

Part A (2 marks)

1.    Body effect coefficient

2.    Equation for the channel length modulation effect in NMOS transistors

3.    Advantages of SOI CMOS process

4.    Compare NMOS and PMOS devices

5.    Compare enhancement and depletion mode devices

6.    Compare CMOS and bipolar technology

7.    Stick diagram for an n-type enhancement mode transistor

8.    List any two types of layout design rules

9.    Different tools availa]ble in a typical CAD tool set.

10. Draw the schematic diagram of the Tristate inverter

11. Different MOS layers

12. Steps involved in the process of IC fabrication

13. Body effect

14. Manufacturing issues

15. Stick diagram of CMOS NOR gate

Part B (8 or 16 marks)

1.    N-well process

2.    Mask layout

3.    Basic operations of nmos transistor

4.    Ideal VI characteristics

5.    Enhancement process

6.    Secondary order effects

7.    DC characteristics

8.    Manufacturing techniques

9.    Design rules for cmos inverter

L-2

Part A (2 marks)

1.    Influence of voltage scaling in power and delay

2.    Express T_PHL and T_PLH in terms of C_load

3.    Expressions for the logical effort and parasitic delay of n input NOR gate.

4.    Why does interconnect increase the circuit delay?

5.    Latch-up problem in CMOS circuits

6.    How do you prevent Latchup problem?

7.    Rise time and fall time

8.    Expression for power dissipation in CMOS inverter

9.    Body effect

10. When the channel said to be pinched-off?

11. Difference between pass transistor and transmission gate

12. Any 4 SPICE card with its functionality

Part B (8 or 16 marks)

1.    Static and dynamic power dissipation

2.    Delay estimation, logical effort and transistor sizing

3.    Parameters affected on scaling

4.    Tradeoffs of MOS transistor models utilized in SPICE

5.    Device models

6.    Circuit characterization

7.    Design margin

8.    Reliability problems

L-3

Part A (2 marks)

1.    Draw the circuit diagram of a CMOS bistable element and its time domain behavior

2.    CMOS transmission gate logic

3.    Draw a pseudo NMOS inverter

4.    Advantages of differential flip flop

5.    Expressions for rise time and fall time in CMOS inverter circuit

6.    Draw 2:1 MUX using Transmission gate

7.    Pull down device

8.    Bubble pushing

9.    Draw XOR gate and XNOR using transmission gates

10. Dual rail logic and example

11. Draw Bi-CMOS circuit and list 2 advantages over CMOS

12. Max delay and min delay failures

13. Strong 0 and weak 0

14. Clockskew

Part B (8 or 16 marks)

1.    Gu and gd for high skew, low skew and pseudo nmos nand gates

2.    Effect of metastability in a bi-stable element

3.    Logic efforts and parasitic delays of AOI22 gates

4.    Various types of dynamic circuits and list their uses

5.    4:1 multiplexers with transmission gates

6.    Comparisons between circuit families

7.    D latch and D FF

8.    Techniques to optimize static CMOS inverter

9.    Dynamic cmos, domino and NP domino logic

10. Sequencing methods

11. Sequencing in traditional domino and skew tolerant domino

12. Principle of low power logic design

13. Characteristics of cmos transmission gates

L-4

Part A (2 marks)

1.    Objective of functionality test

2.    Test fixtures required to test a chip

3.    Aim of adhoc test techniques

4.    Compare functionality test manufacturing test

5.    Need for testing

6.    List the design steps required for testing in CMOS chip design

7.    Two different type of CMOS testing

8.    List any two faults that occur during manufacturing

9.    Different phases of VLSI design flow

10. Basic principle of electronic testing

11. State all the test vectors to test 3 input NAND gate

12. Draw the boundary scan input logic diagram

13. List the techniques of ad-hoc testing

14. IDDQ testing

15. Stuck-at-1 and Stuck-at-0 fault

Part B (8 or 16 marks)

1.    Adhoc testing and scan based approaches

2.    Boundary scan architecture

3.    Manufacturing test principles

4.    BIST

L-5

Part A (2 marks)

1.    Write the Verilog module for an half adder

2.    Delay specifications available in Verilog HDL for modeling a logic gate

3.    Continuous assignment statement in Verilog HDL

4.    Task in Verilog

5.    Syntax for architecture in Verilog HDL

6.    Component declaration

7.    Conditional and procedural assignment

8.    Why do you require sensitivity list?

9.    Difference between task and function

10. Difference between === and ==

11. List the bitwise and reduction operators with examples

12. Types of procedural assignments with examples

Part B (8 or 16 marks)

1.    Conditional and loopting statements

2.    Continuous and implicit continuous assignment

3.    How is Component instantiation bound

4.    Incremental binding

5.    Gate level modeling

6.    Main purpose of test bench

7.    Waveform generation

Important Verilog HDL programs:

1.    Half adder

2.    Full adder

a.    1-bit full adder (using component instantiation)

b.    8-bit full adder using 1-bit full adder

3.    Ripple carry adder

a.    4-bit ripple carry full adder

4.    MUX

a.    4:1 MUX using NAND gate

b.    8:1 MUX

5.    Decoder

a.    3:8 decoder

6.    Priority encoder

a.    4 bit priority encoder

7.    Bit comparator

8.    D-latch

 

PART - A ( 2 marks)

1. What are the different MOS layers?

2. What are the two types of layout design rules?

3. Define rise time and fall time.

4. What is a pull down device?

5. What is mean by “Epitaxy”?

6. What is isolation?

7. What are the steps involved in manufacturing of IC?

8. What is the special feature of Twin-Tub process?

9. Draw the Isotropic etching process diagram.

10. What is silicide?

11. What is AOI?

12. Define fabrication process.

13. Draw the graph of n-MOS depletion mode.

14. Draw the Dc transfer characteristics curve.

11. Define noise margin.

15. Draw the symbol for tristate inverter.

16. Differentiate the nMOS from pMOS.

17. What are all the factors can be extracted from the Vth equation.

18. Define the Power dissipation

19. Define bit and byte.

20 Define FSM.

21 What do you mean by Data flow model?

22. Define Mealy network.

23. What is component in VHDL?

24 Which MOS can pass logic 1 and logic 0 strongly?

25 What is AOI logic function.

26 What are the methods for programming the PALs?

27 What are all the types of programming PALs?

28 Define PLD.

29 Draw the basic PLA.

30 Differentiate the PLA from the PAL.

31. Define test bench.

32. What is FPGA?

33. What is super buffer?

34. What is meant by Steering logic?

35. Give the advantages and disadvantages of SOI.

PART-B (16&8 Marks)

1. Differentiate the p-well CMOS process from n-well CMOS process. Explain the n-well CMOS process to fabricate the n-switches.

2. Discuss the steps involved in IC fabrication process.

3. Describe n-well process in detail.

4. Explain the DC characteristics of CMOS inverter with neat sketch.

5. Explain channel length modulation and body effect.

6. Explain the different regions of operation in a MOS transistor.

7. Write a note on MOS models.

8. Explain in detail any five operators used in VHDL.

9. Write the VHDL code for 4 bit ripple carry full adder.

10. Give the structural description for priority encoder using VHDL.

11 List out the layout design rule. And draw the physical layout for one basic gate and two universal gates.

12 Explain the n MOS and p MOS enhancement transistor with its physical structure.

13. Derive and explain the

(I) Threshold voltage equation,

(II) MOS DC equation.

14. Explain the complimentary CMOS inverter DC characteristics.

15. Write short notes on

(I) Noise Margin,

(II) Rise Time,

(III) Fall Time.

16. Develop the project using VHDL to realize the function of a ripple carry adder and draw its RTL.

17. Design a full adder by cascading two half adders and develop a project to realize it in model simulator 6.0.

18 Briefly explain the following terms

(i) Design of switches with MOSFETs,

(ii) Transmission gate,

(iii) Muxs using TG.

19. Draw the physical layout for the following Boolean expression

a. y = (a +b)’ + c + de

b. x = (lmnop)’ + q’(r’s + rs’)

20. Differenced the PALs from PLAs. And explain the 22V10 standard logic structure with the architecture.

21. Explain the methods used to programme the PALs with neat diagram.

22. Explain the Field programmable gate array with the architecture and logic blocks.

23. Draw and explain the typical architecture of PAL.

24. Explain test bench with an example and ways of generating waveforms.

25. Write a VHDL description to design Flip Flops( RS, JK, D, T) and write its test bench.

26. Write a VHDL description to design 8:1 MUX using two 4:1 MUX.

27. Write a VHDL description to design 8:1 MUX and DEMUX.

28. Write a VHDL description to design a undown counter and write its test bench.

29. Explain type,Operators, timing controls, Procedural assignments.

30 Draw and explain with diagrams tally circuits.

31. Draw and explain barrel shifters.

32. Explain with neat diagrams dynamic CMOS clocking.

33. Derive an expression for pull up and pull down ratio for transistors.

34. Describe in detail the chip with programmable logic structures.

35. Explain packages in vhdl with example.

36. With neat diagram explain finite state machine PLA.

37. Expain structured design of combinational circuits- EXOR Structure, Multiplex Structure.

39. Discuss the steps involved in fabrication of BICMOS technology.