VHDL Code for 4-bit Comparator

4-bit comparator using data flow model:

use IEEE.STD_LOGIC_1164.all;

entity \4_bit\ is

           port(

                    a : in STD_LOGIC_VECTOR(0 to 3);

                    b : in STD_LOGIC_VECTOR(0 to 3);

                    agtb : out STD_LOGIC;

                    aeqb : out STD_LOGIC;

                    altb : out STD_LOGIC

               );

end \4_bit\;

architecture \4_bit_data\ of \4_bit\ is

begin

aeqb <= '1' when a=b else '0';

agtb<= '1' when a>b else '0';

altb <= '1' when a<b else'0';

                    

end \4_bit_data\;    

4-bit comparator using  behavioral  style model:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity \4_comp\ is

           port(

                    a : in STD_LOGIC_VECTOR(0 to 3);

                    b : in STD_LOGIC_VECTOR(0 to 3);

                    agtb : out STD_LOGIC;

                    altb : out STD_LOGIC;

                    aeqb : out STD_LOGIC

               );

end \4_comp\;

architecture \4_comp_beh\ of \4_comp\ is

begin 

          process(a,b)

          begin

                   if(a>b) then

                             agtb<= '1';

                             aeqb<='0';

                             altb<= '0';                                           

                             elsif(a<b) then

                             agtb<= '0';

                             aeqb<='0';

                             altb<= '1';

                             elsif(a=b)then

                             agtb<= '0';

                             aeqb<='1';

                             altb<= '0';

                             end if;

                             end process;

                            

                   end \4_comp_beh\;

4-bit comparator using  structural style model:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity \4_comp_stru\ is

           port(

                    a : in STD_LOGIC_VECTOR(0 to 3);

                    b : in STD_LOGIC_VECTOR(0 to 3);

                    aeqb : inout STD_LOGIC;

                    agtb : inout STD_LOGIC;

                    altb : out STD_LOGIC

               );

end \4_comp_stru\;

architecture \4_comp_str\ of \4_comp_stru\ is

          component xnor2

                   port(l,m: in std_logic;n: out std_logic);

          end component;

          component and2

                   port(x,y: in std_logic; z: out std_logic);

          end component;

          component inv

                   port (u: in std_logic; v: out std_logic);

          end component;

          component and3

                   port(l,m,o: in std_logic;n: out std_logic);

          end component;

          component or4

                   port(m1,m2,m3,m4: in std_logic; mf: out std_logic);

          end component;

          component and4

                   port(q1,q2,q3,q4: in std_logic; qf: out std_logic);

          end component;

          component and5

                   port (e1,e2,e3,e4,e5: in std_logic; ef: out std_logic);

          end component;

          component nor2

                   port(l1,l2: in std_logic; lf: out std_logic);

          end component;

          signal i0,i1,i2,i3,j0,j1,j2,j3,j4,j5,h0,h1,h2,h3: std_logic;

          begin

                   m1: inv port map (b(3),i3);

                   m2: inv port map (b(2),i2);

                   m3: inv port map (b(1),i1);

                   m4: inv port map (b(0),i0);

                   m5: xnor2 port map (a(3),b(3),j3);

                   m6: xnor2 port map (a(2),b(2),j2);

                   m7: xnor2 port map (a(1),b(1),j1);

                   m8: xnor2 port map (a(0),b(0),j0);

                   m9: and2 port map (a(3),i3,h3);

                   m10: and3 port map (a(2),i2,j3,h2);

                   m11: and4 port map (a(1),i1,j2,j3,h1);

                   m12: and5 port map (a(0),i0,j1,j2,j3,h0);

                   m13: and4 port map (j0,j1,j2,j3,aeqb);

                   m14: or4 port map (h0,h1,h2,h3,agtb);

                   m15: nor2 port map (aeqb,agtb,altb);

end \4_comp_str\;